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Table D-1 · Verification Testbench Tests (Continued)
142
Test
45
60
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
71
98
99
S..n
Q
Description
DMA Mega Test; multiple DMA tests at the same time
Master Mode Test
DMA Single Transfer Test with DMA completion interrupt enabled
DMA Poll Status Test with DMA completion interrupt enabled
DMA Transfer Test with Busy_Master assertion
DMA Transfer Test with Stall_Master assertion
Byte Enable Test with DMA transfers
Byte Enable Test on Backend Registers
DMA with Maximum Transfer Length
DMA Dataflow with variable transfer rates and FIFO recovery
DMA Burst Length Tests with FIFO recovery
DMA Auto Transfer Test with FIFO recovery; checks DMA starting and stopping conditions.
Fast Master Back-to-Back Test, DMA termination and another Master accessing the core
immediately.
Direct Mode DMA Transfer Test
Miscellaneous DMA Tests
Backend Configuration Access Tests
Master Mode Test
User DMA Routine
Quick Test (all slots)
Exhaustive Tests (all tests / all slots)
Test 00–99 on Slot S (e.g., 112)
Quit Testbench
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